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rev. 1.5 6/08 copyright ? 2008 by silicon laboratories si5023 si5017 oc-48/stm-16 sonet/sdh cdr ic with l imiting a mplifier features h igh-speed clock and data recovery devic e with integrated limiting amplifier: applications description the si5017 is a fully-integrated, hi gh-performance limiting amplifier (la) and clock and data recovery (cdr) ic for high-speed serial communication systems. it derives timing information and data from a serial input at oc-48 and stm-16 rates. support for 2.7 gbps data streams is also provided for oc -48/stm-16 applications that employ forward error correction (fec). use of an external reference clock is optional. silicon laboratories dspl l? technology elim inates sensitive noise entry points, thus making the pll less susceptible to board-level interaction and helping to ensure optimal jitter performance. the si5017 represents a new standard in low jitter, low power, small size, and integration for high-speed la/cdrs. it operates from a 3.3 v supply over the industrial temperature range (?40 to 85 c). functional block diagram ? supports oc-48/stm-16 and 2.7 gbps fec ? dspll ? technology ? jitter generation 3.0 mui rms (typ) ? small footprint: 5 x 5 mm ? loss-of-signal level alarm ? data slicing level control ? 10 mv pp differential sensitivity ? 3.3 v supply ? reference and reference-less operation supported ? sonet/sdh/atm routers ? add/drop multiplexers ? digital cross connects ? board level serial links ? sonet/sdh test equipment ? optical transceiver modules ? sonet/sdh regenerators limiting amp dspll lock detection retimer reset/ calibration bias gen. buf buf clkout+ clkout? din+ din? refclk+ refclk? (optional) los lol rext reset/cal slice_lvl dsqlch clk_dsbl ltr signal detect los_lvl ber_lvl ber monitor dout+ dout? 2 2 2 2 ber_alm ordering information: see page 22. pin assignments si5017 gnd pad 1 2 3 4 5 vdd los_lvl refclk+ vdd slice_lvl 6 7 lol refclk? 21 20 19 18 17 rext reset/cal dout+ vdd vdd 16 15 tdi dout? 8 9 10 11 12 los dsqlch din+ ltr vdd 13 14 vdd din? 28 27 26 25 24 ber_alm ber_lvl clkdsbl nc vdd 23 22 clkout? clkout+
si5017 2 rev. 1.5
si5017 3 rev. 1.5 t able of c ontents section page 1. detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3. typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.1. limiting amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2. dspll ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.3. operation without an ex ternal reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4. operation with an external refer ence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.5. lock detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.6. lock-to-reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.7. loss-of-signal (los) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.8. bit-error-rate (ber ) detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.9. data slicing level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.10. pll performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.11. reset/dspll calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.12. clock disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 4.13. data squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 4.14. device grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.15. bias generation circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.16. voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.17. differential input ci rcuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.18. differential output circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5. pin descriptions: si5017 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7. top mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 8. package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
si5017 4 rev. 1.5 1. detailed block diagram slicing control signal detect phase detector a/d limiting amp n dsp vco clk dividers lock detection retime ber monitor din+ din+ refclk (optional) ltr slice_lvl los_lvl calibration reset/cal clkout+ dout+ clkout? dout? clkdsbl ber_alm ber_lvl los lol dsqlch bias generation rext
si5017 rev. 1.5 5 2. electrical specifications figure 1. differential voltage measurement (din, refclk, dout, clkout) figure 2. clock to data timing table 1. recommended operating conditions parameter symbol test condition min 1 typ max 1 unit ambient temperature t a ?40 25 85 c si5017 supply voltage 2 v dd 3.135 3.3 3.465 v notes: 1. all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25 c unless otherwise stated. 2. the si5017 specifications are guarant eed when using the recommended application circuit (including component tolerance) of the "3. typical a pplication schematic" on page 11. 0.5 v id signal+ signal? v id b. operation with differential inputs and outputs v is a. operation with single-ended inputs signal+ signal? v t v t (signal+) ? (signal?) dout t cr-d t cf-d clkout
si5017 6 rev. 1.5 figure 3. dout and clkout rise/fall times figure 4. pll acquisition time figure 5. los response time dout, clkout t f t r 80% 20% t aq reset/cal lol datain t aq lol datain los threshold level t los los
si5017 7 rev. 1.5 table 2. dc characteristics (v dd = 3.3 v 5%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit supply current 1 fec (2.7 gbps) oc-48 i dd ? ? 173 170 184 180 ma power dissipation fec (2.7 gbps) oc-48 p d ? ? 571 561 637 623 mw common mode input voltage (din) 2 v icm see figure 11 1.30 1.50 1.62 v common mode input voltage (refclk) 2 v icm see figure 10 1.90 2.10 2.30 v din single-ended input voltage swing 2 v is see figure 1a 10 ? 500 mv din differential input voltage swing 2 v id see figure 1b 10 ? 1000 mv refclk single-ended input voltage swing 2 v is see figure 1a 200 ? 750 mv refclk differential input voltage swing 2 v id see figure 1b 200 ? 1500 mv input impedance (din) r in line-to-line 84 100 116 ? differential output voltage swing (dout) v od 100 ? load line-to-line 700 800 1000 mv pp differential output voltage swing (clkout) v od 100 ? load line-to-line 700 800 1100 mv pp output common mode voltage (dout) v ocm 100 ? load line-to-line 1.6 1.95 2.35 v output common mode voltage (clkout) v ocm 100 ? load line-to-line 1.6 1.80 2.35 v output impedance (dout,clkout) r out single-ended 84 100 116 ? input voltage low (lvttl inputs) v il ?? .8 v input voltage high (lvttl inputs) v ih 2.0 ? ? v input low current (lvttl inputs) i il ??10a input high current (lvttl inputs) i ih ??10a input impedance (lvttl inputs) r in 9??k ? los_lvl, ber_lvl, slice_lvl input impedance r in 50 100 125 k ? output voltage low (lvttl outputs) v ol i o =2ma ? ? 0.4 v output voltage high (lvttl outputs) v oh i o =2ma 2.0 ? ? v notes: 1. no load on lvttl outputs. 2. these inputs may be driven differentially or single-endedl y. when driven single-endedly, the unused input must be ac coupled to ground.
si5017 8 rev. 1.5 table 3. ac characteristics (clock and data) (v dd = 3.3 v 5%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit output clock rate f clk 2.4 ? 2.7 ghz output clock rise time t r figure 3 ? 70 90 ps output clock fall time t f figure 3 ? 70 90 ps output clock duty cycle 48 50 52 % of ui output data rise time t r figure 3 ? 80 110 ps output data fall time t f figure 3 ? 80 110 ps clock to data delay fec (2.7 gbps) oc-48 t cr-d figure 2 190 190 230 230 265 265 ps clock to data delay fec (2.7 gbps) oc-48 t cf-d figure 2 ?70 ?60 ?40 ?30 ?10 0 ps input return loss 100 khz?1.5 ghz 1.5 ghz?4.0 ghz ?15 ?10 ? ? ? ? db db slicing level offset (relative to the in ternally set input common mode voltage) v slice slice_lvl = 750 mv to 2.25 v see figure 8 on page 14. loss-of-signal range * (peak-to-peak differential) v los los_lvl = 1.50 to 2.50 v 0 ? 40 mv loss-of-signal response time t los figure 5 8 20 25 s *note: adjustment voltage is calculated as follows: v los = (los_lvl ? 1.50)/25.
si5017 9 rev. 1.5 table 4. ac characteristics (pll characteristics) (v dd =3.3 v 5%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit jitter tolerance (oc-48)* j tol(pp) f = 600 hz 40 ? ? ui pp f = 6000 hz 4 ? ? ui pp f = 100 khz 3 ? ? ui pp f = 1 mhz 0.3 ? ? ui pp rms jitter generation * j gen(rms) with no jitter on serial data ? 3.0 5.0 mui peak-to-peak jitter generation * j gen(pp) with no jitter on serial data ? 25 55 mui jitter transfer bandwidth * j bw oc-48 ? ? 2.0 mhz jitter transfer peaking * j p ?0.030.1db acquisition time (reference clock applied) t aq after falling edge of reset/cal ?1.62.2ms from the return of valid data 20 100 500 s acquisition time (reference-less operation) t aq after falling edge of reset/cal ?2.05.5ms from the return of valid data 1.5 2.5 5.5 ms reference clock range see table 7 on page 13. f clk / 16 f clk / 32 f clk / 128 ? ? ? 155.52 77.76 19.44 ? ? ? mhz input reference clock frequency tolerance c tol ?500 ? +500 ppm frequency difference at which receive pll goes out of lock (refclk compared to the divided down vco clock) ?650 ?ppm *note: as defined in bellcore specifications: gr-253- core, issue 3, septem ber 2000. using prbs 2 23 ? 1 data pattern.
si5017 10 rev. 1.5 table 5. absolute maximum ratings parameter symbol value unit dc supply voltage v dd ?0.5 to 3.5 v lvttl input voltage v dig ?0.3 to 3.6 v differential input voltages v dif ?0.3 to (v dd + 0.3) v maximum current any output pin 50 ma operating junction temperature t jct ?55 to 150 c storage temperature range t stg ?55 to 150 c esd hbm tolerance (100 pf, 1.5 k ? )1kv note: permanent device damage may occur if the above absolu te maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 6. thermal characteristics parameter symbol test condition value unit thermal resistance junction to ambient ? ja still air 38 c/w
si5017 rev. 1.5 11 3. typical application schematic si5017 lvttl control inputs loss-of-lock indicator ltr clkdsbl lol high-speed serial input system reference clock (optional) din+ din? refclk+ refclk? rext vdd gnd dout+ dout? clkout+ clkout? recovered data recovered clock 100 pf x 4 0.1 ? f vdd reset/cal dsqlch ber alarm indicator ber_alm loss-of-signal indicator los 10 k ? (1%) slice_lvl data slice level set ber_lvl bit error rate level set los_lvl loss-of-signal level set
si5017 12 rev. 1.5 4. functional description the si5017 integrates a high-speed limiting amplifier with a cdr unit that operates between 2.4 and 2.7 gbps. no external reference clock is required for clock and data recovery. the limiting amplifier magnifies very low-level input data signals so accurate clock and data recovery can be performed. the cdr uses silicon laboratories dspll ? technology to recover a clock synchronous to the input data stream. the recovered clock retimes the incoming data, and both are output synchronously via current-mode logic (cml) drivers. silicon laboratories? d spll technology ensures superior jitter performance while eliminating the need for external loop filter components found in traditional phase-locked loop (pll) implementations. the limiting amplifier incl udes a control input for adjusting the data slicing le vel and provides a loss-of- signal level alarm output. the cdr includes a bit-error- rate performance monitor which signals a high bit-error- rate condition (associated with excessive incoming jitter) relative to an extern ally adjustable bit-error-rate threshold. the optional reference clock minimizes the cdr acquisition time and provides a stable reference for maintaining the output clock when locking to reference is desired. 4.1. limiting amplifier the limiting amplifier accept s the low-level signal output from a transimpedance amplifier (tia). the low-level signal is amplified to a usable level for the cdr unit. the minimum input swing requirement is specified in table 2. larger input amplitudes (up to the maximum input swing specified in table 2) are accommodated without degradation of performance. the limiting amplifier ensures optimal data slicing by using a digital dc offset cancellation technique to remove any dc bias introduced by the amplification stage. 4.2. dspll ? the si5017 pll structure (shown in the "1. detailed block diagram" on page 4) utilizes silicon laboratories' dspll technology to maintain superior jitter performance while eliminating the need for external loop filter components found in traditional pll implementations. this is achieved using a digital signal processing (dsp) algorithm to replace the loop filter commonly found in analog pll designs. this algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage-controlled oscillato r (vco). this technology enables cdr with far less jitte r than is generated using traditional methods, and it eliminates performance degradation caused by external component aging. in addition, because external loop filter components are not required, sensitive noise entry points are eliminated, thus making the dspll less susceptible to board-level noise sources and making sonet/sdh jitter compliance easier to atta in in the application. 4.3. operation without an external refer- ence the si5017 can perform clock and data recovery without an external refe rence clock. tying the refclk+ input to vdd and the refclk? input to gnd configures the device to operate without an external reference clock. clock recovery is achieved by monitoring the timing quality of the incoming data relative to the vco frequency. lock is maintained by continuously monitoring the incoming data timing quality and adjusting the vco accordingly. details of the lock detection and the lock-to-reference functions while in this mode are described in their respective sections below. note: without an external reference the acquisition of data is dependent solely on the data itself and typically requires more time to acquire lock than when a refer- ence is applied. 4.4. operation with an external reference the si5017 can also perform clock and data recovery with an external reference. the device?s optional external reference clock centers the dspll, minimizes the acquisition time, and main tains a stable output clock (clkout) when lock-to-reference (ltr ) is asserted. when the reference clock is present, the si5017 uses the reference clock to center the vco output frequency so that clock and data are recovered from the input data stream. the device self configures for operation with one of three reference clock frequencies. this eliminates the need to externally configure the device to operate with a particular reference clock. the reference clock centers the vco for a nominal output between 2.5 and 2.7 ghz. the vco frequency is centered at 16, 32, or 128 times the reference clock frequency. detection circuitry continuously monitors the reference clock input to determine whether the device should be configured for a reference clock that is 1/16, 1/32, or 1/128 the nominal vco output. approximate reference clock frequencies for some target applications are given in table 7.
si5017 13 rev. 1.5 4.5. lock detect the si5017 provides lock-detect circuitry that indicates whether the pll has achieved frequency lock with the incoming data. the operation of the lock-detector depends on the reference clock option used. when an external reference clock is provided, the circuit compares the frequency of a divided-down version of the recovered clock with the frequency of the applied reference clock (refclk). if the recovered clock frequency deviates from that of the reference clock by the amount specified in table 4 on page 9, the pll is declared out of lock, and the loss-of-lock (lol ) pin is asserted. in this state, th e pll will periodically try to reacquire lock with the incoming data stream. during reacquisition, the recovered clock frequency (clkout) drifts over a 600 ppm range relative to the applied reference clock and the lol output alarm may toggle until the pll has reacquired frequency lock. due to the low noise and stability of the dspll, th ere is the possibility that the pll will no t drift enough to render an out-of-lock condition, even if the data is removed from inputs. in applications requiring a more stable output clock during out-of-lock conditions, the lock-to-reference (ltr ) input can be used to force the pll to lock to the externally supplied reference. in the absence of an external reference, the lock detect circuitry uses a data quality measure to determine when frequency lock has been lost with the incoming data stream. during reacquisition, clkout may vary by approximately 10% from the nominal data rate. 4.6. lock-to-reference the ltr input is used to force a stable output clock when an alarm condition, like los, exists. in typical applications, the los output is tied to the ltr input to force a stable output clock when the input data signal is lost. when ltr is asserted, the dspll is prevented from acquiring the data signal present on din. the operation of the ltr control input depends on which reference clocking mode is used. when an external reference clock is present, assertion of ltr forces the dspll to lock clkout to the provided reference. if no external reference clock is used, ltr forces the dspll to hold the digital frequency control input to the vco at the last value. this produces a stable output clock as long as supply and temperature are constant. 4.7. loss-of-signal (los) the si5017 indicates a loss-of-signal condition on the los output pin when the input peak-to-peak signal level on din falls below an externally controlled threshold. the los threshold range is specified in table 3 and is set by applying a voltage on the los_lvl pin. the graph in figure 6 illustrate s the los_lvl mapping to the los threshold. the los output is asserted when the input signal drops below the programmed peak-to- peak value. if desired, the los function may be disabled by grounding los_lvl or by adjusting los_lvl to be less than 1 v. note: the los circuit is designed to only work with pseudo- random, dc-balanced data. figure 6. los_lvl mapping figure 7. los signal hysteresis table 7. typical refclk frequencies sonet/sdh oc-48 with 15/14 fec ratio of vco to refclk 19.44 mhz 20.83 mhz 128 77.76 mhz 83.31 mhz 32 155.52 mhz 166.63 mhz 16 40mv/v 0 mv 0 v los_lvl (v) los threshold (mv pp ) 30 mv 2.25 v 1.50 v 1.00 v 15 mv los disabled los undefined 1.875 v 40 mv 2.50 v los limited by device noise 9 3 los los_lvl r1 r2 10k si5017 cdr los alarm set los level
si5017 14 rev. 1.5 in many applications it is desirable to produce a fixed amount of signal hysteresis for an alarm indicator such as los , since a marginal data input signal could cause intermittent toggling, leading to false alarm status. when it is anticipated that very low-level din signals will be encountered, the introduction of an adequate amount of los hysteresis is recommended to minimize any undesirable los signal toggling. figure 7 illustrates a simple circuit that may be used to set a fixed level of los signal hysteresis for the si5017 cdr. the value of r1 may be chosen to provide a range of hysteresis from 3 to 8 db where a nominal value of 800 ? adjusts the hysteresis level to approximately 6 db. use a value of 500 ? or 1000 ? for r1 to provide 3 db or 8 db of hysteresis, respectively. hysteresis is defined as the ratio of the los deassert level (losd) and the los assert level (losa). the hysteresis in decibels is calculated as 20log(losd/ losa). 4.8. bit-error-ra te (ber) detection the si5017 uses a proprietary silic on laboratories algorithm to generate a bit-error-rate (ber) alarm on the ber_alm pin if the observed ber is greater than a user programmable threshold. bit error detection relies on the input data edge timing; edges occurring outside of the expected event window are counted as bit errors. the ber threshold is programmed by applying a voltage to the ber_lvl pin between 500 mv and 2.25 v corresponding to a ber of approximately 10?10 and 10?6, respectively. the voltage present on ber_lvl maps to the ber as follows: log10(ber) = (4 x ber_lvl) ? 13. (ber_lvl is in volts; ber is in bits per second.). 4.9. data slicing level the si5017 provides the ability to externally adjust the slicing level for applications that require bit-error-rate (ber) optimization. adjust ments in slicing level of 25 mv (typical, relative to the internally set input common mode voltage) are supported. the slicing level is set by applying a voltage between 0.75 and 2.25 v to the slice_lvl input. see figure 8 for the operation levels of the slice circuit. when slice_lvl is driven below 500 mv, the slicing level adjustment is disabled, and the slicing level is set to the cross-point of the differential input signal. note: the slice circuit is designed to only work with pseudo- random, dc-balanced data. figure 8. si5017 oc-48 slice specification -40 -30 -20 -10 0 10 20 30 40 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 not specified slice disable 10 mv 10 mv note: slice is a continuous curve. this chart shows the range of results from part-to-part.
si5017 15 rev. 1.5 4.10. pll performance the pll implementation used in the si5017 is fully compliant with the jitter specifications proposed for sonet/sdh equipment by bellcore gr-253-core, issue 3, september 2000 and itu-t g.958. 4.10.1. jitter tolerance the si5017?s tolerance to input jitter exceeds that of the bellcore/itu mask shown in figure 8. this mask defines the level of peak-to-peak sinusoid jitter that must be tolerated when applied to the differential data input of the device. 4.10.2. jitter transfer the si5017 exceeds all relevant bellcore/itu specifications related to sonet/sdh jitter transfer. jitter transfer is defined as th e ratio of output signal jitter to input signal jitter as a function of jitter frequency. these measurements are made with an input test signal that is degraded with sinusoidal jitter whose magnitude is defined by the mask in figure 9. figure 9. jitter transfer specification 4.10.3. jitter generation the si5017 exceeds all relevant specifications for jitter generation proposed for sonet/sdh equipment. the jitter generation specification defines the amount of jitter that may be present on the recovered clock and data outputs when a jitter free input signal is provided. the si5017 typically generates less than 3.0 mui rms of jitter when presented with ji tter-free input data. 4.11. reset/dspll calibration the si5017 achieves opti mal jitter performance by automatically calibrating the loop gain parameters within the dspll on powerup. calibration may also be initiated by a high-to-low transition on the reset/cal pin. the reset/cal pin must be held high for at least 1 s. when reset/cal is rele ased (set to low) the digital logic resets to a known initial condition, recalibrates the dspll, and begins to lock to the incoming data stream. for a valid reset to occur when using reference mode, a proper, external reference clock frequency must be applied as specified in table 7. 4.12. clock disable the si5017 provides a clock disable pin (clk_dsbl) that is used to disable the recovered clock output (clkout). when the clk_dsbl pin is asserted, the positive and negative terminals of clkout are tied to vdd through 100 ?? on-chip resistors. 4.13. data squelch the si5017 provides a dat a squelching pin (dsqlch) that is used to set the reco vered data output (dout) to binary zero. when the dsqlch pin is asserted, the dout+ signal is held low and the dout? signal is held high. this pin can be is used to squelch corrupt data during los and lol situations. care must be taken when ac coupling these outputs; a long string of zeros or ones will not be held thr ough ac coupling capacitors. 4.14. device grounding the si5017 uses the gnd pad on the bottom of the 28- pin micro leaded package (qfn) for device ground. this pad should be connected directly to the analog supply ground. see figure 15 on page 19 and figure 16 on page 23 for the ground (gnd) pad location. 4.15. bias generation circuitry the si5017 makes use of an external resistor to set internal bias currents. the external resistor allows precise generation of bias currents which significantly reduces power consumption versus traditional implementations that use an internal resistor. the bias generation circuitry requires a 10 k ? (1%) resistor connected between rext and gnd. 4.16. voltage regulator the si5017 operates from a 3.3 v external supply voltage. internally the device operates from a 2.5 v supply. the si5017 regulates 2.5 v internally down from the external 3.3 v supply. in addition to supporting 3.3 v systems, the on-chip linear regulator offers be tter power supply noise rejection versus a direct 2.5 v supply. 0.1 db jitter transfer fc frequency 20 db/decade slope fc (khz) sonet data rate oc-48 2000 acceptable range
si5017 16 rev. 1.5 4.17. differential input circuitry the si5017 provides differential inputs for both the high-speed data (din) and the reference clock (refclk) inputs. an example termination for these inputs is shown in figures 10 and 11, respectively. in applications where direct dc coupling is possible, the 0.1 f capacitors ma y be omitted. (los operation is only guaranteed when ac coupled.) the data input limiting amplifier requires an input signal with a differential peak-to-peak voltage as specified in table 2 on page 7 to ensure a ber of at least 10 ?12 . the refclk input differential peak-to-peak voltage requirement is also specified in table 2. figure 10. input termination for refclk (ac coupled) figure 11. input termination for din (ac coupled) clock source si5017 0.1 ? f 0.1 ? f zo = 50 ? zo = 50 ? rfclk + rfclk ? 2.5 k ? 2.5 k ? 10 k ? 10 k ? 100 ? gnd 2.5 v (5%) tia si5017 0.1 ? f 0.1 ? f zo = 50 ? zo = 50 ? din+ din? 5 k ? 50 ? gnd 7.5 k ? 50 ? 2.5 v (5%)
si5017 17 rev. 1.5 figure 12. single-ended input termination for refclk (ac coupled) figure 13. single-ended input termination for din (ac coupled) 0.1 ? f clock source si5017 0.1 ? fzo = 50 ? rfclk + rfclk ? 2.5 k ? 2.5 k ? 10 k ? 10 k ? 50 ? gnd 2.5 v (5%) si5017 0.1 ? f zo = 50 ? din+ din? 5 k ? 50 ? gnd 7.5 k ? 50 ? ? 100 0.1 ? f signal source 2.5 v (5%)
si5017 18 rev. 1.5 4.18. differential output circuitry the si5017 utilizes a cml architectu re to output both the recovered cl ock (clkout) and data (dout). an example of output termination with ac coupling is shown in figure 14. in applications in which direct dc coupling is possible, the 0.1 ? f capacitors may be omitted. the differential peak-to-peak voltage swing of the cml architecture is specified in table 2 on page 7. figure 14. output termination for dout and clkout (ac coupled) dout?, clkout? 50 ? 50 ? 0.1 ? f 0.1 ? f zo = 50 ? zo = 50 ? si5017 vdd vdd 100 ? 100 ? 2.5 v (5%) dout+, clkout+ 2.5 v (5%)
si5017 rev. 1.5 19 5. pin descriptions: si5017 figure 15. si5017 pin configuration table 8. si5017 pin descriptions pin # pin name i/o signal level description 1,2,11,14,18, 21,25 vdd 3.3 v supply voltage. nominally 3.3 v. 3los_lvli los level control. the los threshold is set by the input voltage level applied to this pin. figure 6 on page 13 shows the input setting to output threshold mapping. los is disabled when the voltage applied is less than 1 v. 4 slice_lvl i slicing level control. the slicing threshold level is set by applying a volt- age to this pin as described in the slicing level sec- tion of the data sheet. if this pin is tied to gnd, slicing level adjustment is disabled, and the slicing level is set to the midpoint of the differential input signal on din. slicing level becomes active when the voltage applied to the pin is greater than 500 mv. 5 6 refclk+ refclk? isee table2 differential reference clock (optional). when present, the reference clock sets the center operating frequency of the dspll for clock and data recovery. tie refclk+ to vdd and refclk? to gnd to operate without an external reference clock. see table 7 on page 13 for typical reference clock frequencies. gnd pad 1 2 3 4 5 vdd los_lvl refclk+ vdd slice_lvl 6 7 lol refclk? 21 20 19 18 17 rext reset/cal dout+ vdd vdd 16 15 tdi dout? 8 9 10 11 12 los dsqlch din+ ltr vdd 13 14 vdd din? 28 27 26 25 24 ber_alm ber_lvl clkdsbl nc vdd 23 22 clkout? clkout+
si5017 20 rev. 1.5 7 lol olvttl loss-of-lock. this output is driven low when the recovered clock frequency deviates from the reference clock by the amount specified in table 4 on page 9. if no exter- nal reference is s upplied, this signal will be active when the internal pll is no longer locked to the incoming data. 8 ltr ilvttl lock-to-reference. when this pin is low, the dspll disregards the data inputs. if an external reference is supplied, the out- put clock locks to the supplied reference. if no external reference is used, the dspll locks the control loop until ltr is released. note: this input has a weak internal pullup. 9 los olvttl loss-of-signal. this output pin is driven low when the input signal is below the threshold set via los_lvl. (los opera- tion is guaranteed only when ac coupling is used on the din inputs.) 10 dsqlch lvttl data squelch. when driven high, this pin forces the data present on dout+ to zero and dout? to one. for normal operation, this pin should be low. dsqlch may be used during los/lol conditions to prevent random data from being presented to the system. note: this input has a weak internal pulldown. 12 13 din+ din? isee table2 differential data input. clock and data are recovered from the differential signal present on these pins. ac coupling is recommended. 15 gnd gnd production test input. this pin is used during production testing and must be tied to gnd for normal operation. 16 17 dout? dout+ ocml differential data output. the data output signal is a retimed version of the data recovered from the signal present on din. 19 reset/cal i lvttl reset/calibrate. driving this input high fo r at least 1 s will reset internal device circuitry. a high to low transition on this pin will force a dspl l calibration. for normal operation, drive this pin low. note: this input has a weak internal pulldown. 20 rext external bias resistor. this resistor is used to establish internal bias cur- rents within the device. this pin must be connected to gnd through a 10 k ??? 1 ??? resistor. table 8. si5017 pin descriptions (continued) pin # pin name i/o signal level description
si5017 rev. 1.5 21 22 23 clkout? clkout+ ocml differential clock output. the output clock is recovered from the data signal present on din except when ltr is asserted or the lol state has been entered. 24 clkdsbl i lvttl clock disable. when this input is high, the clkout output drivers are disabled. for normal operation, this pin should be low. note: this input has a weak internal pulldown. 26 ber_lvl i bit error rate level control. the ber threshold level is set by applying a volt- age to this pin. when the ber exceeds the pro- grammed threshold, ber_alm is driven low. if this pin is tied to gnd, ber_alm is disabled. 27 ber_alm olvttl bit error rate alarm. this pin will be driven low to indicate that the ber threshold set by ber_lvl has been exceeded. there is no hysteresis. 28 nc no connect. leave this pin disconnected. gnd pad gnd gnd supply ground. nominally 0.0 v. the gnd pad found on the bottom of the 28-lead qfn (see figure 16 on page 23) must be connected directly to supply ground. minimize the ground path inductance for optimal performance. table 8. si5017 pin descriptions (continued) pin # pin name i/o signal level description
si5017 22 rev. 1.5 6. ordering guide 7. top mark part number package voltage pb-free temperature si5017-x-gm 28-lead qfn 3.3 yes ?40 to 85 c 1. ?x? denotes product revision. 2. add an ?r? at the end of the device to denote tape and reel option; 2500 quantity per reel. 3. these devices use a nipdau pre-plated finish on the leads that is fully rohs6 compliant while being fully compatible with both leaded and lead-free card assembly processes. part number die revision?device type assembly date (yyww) si5017 d-gm yy = year ww = work week
si5017 rev. 1.5 23 8. package outline figure 16 illustrates the package details for the si501 7. table 9 lists the values fo r the dimensions shown in the illustration. for a pad layout recommendat ion please contact s ilicon labo ratories. figure 16. 28-lead quad flat no-lead (qfn) table 9. package diagram dimensions controlling dimension: mm symbol millimeters min nom max a 0.800.850.90 a1 0.00 0.02 0.05 b 0.180.250.30 d 5.00 bsc d2 2.95 3.10 3.25 e 0.50 bsc e 5.00 bsc e2 2.95 3.10 3.25 l 0.500.600.70 ? 0 ? 12 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.05 notes: 1. 1.all dimensions shown are in m illimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jede c outline mo-220, variation vhhd-1. 4. recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
si5017 24 rev. 1.5 d ocument c hange l ist revision 0.1 to revision 1.0 ? added figure 4, ?pll acquisition time,? on page 6. ? table 2 on page 7 ?? added fec (2.7 ghz) supply current ?? updated values: supply current ?? added fec (2.7 ghz) power dissipation ?? updated values: power dissipation ?? updated values: common mode input voltage (refclk) ?? updated values: output common mode voltage ? table 3 on page 8 ?? added separate output clock rise time ?? added separate output clock fall time ?? updated values: output clock rise time ?? updated values: output clock fall time ? table 4 on page 9 ?? updated values: jitter tolerance (oc-48) for f = 1 mhz ?? updated values: acquisition time (reference clock applied) ?? updated values: acquisition time (reference-less operation) ?? updated values: freq difference at which receive pll goes out of lock ?? updated values: freq difference at which receive pll goes into lock ? removed ?hysteresis dependency? figure. ? added figure 7, ?los signal hysteresis,? on page 13. ? corrected error: table 8 on page 19?changed description for los_lvl from ?los is disabled when the voltage applied is less than 500 mv? to ?los is disabled when the voltage applied is less than 1.0 v.? revision 1.0 to revision 1.1 ? corrected ?revision 0.1 to revision 1.0? change list. revision 1.1 to revision 1.2 ? added figure 5, ?los response time,? on page 6. ? updated table 2 on page 7 ?? added ?output common mode voltage (dout)? with updated values. ?? added ?output common mode voltage (clkout)? with updated values. ? table 3 on page 8. ?? added ?output clock duty cycle? ?? added ?loss-of-signal response time? ? updated table 8 on page 19 ?? changed ?clock input? to ?din inputs? for loss-of-signal. ? updated figure 16, ?28-lead quad flat no-lead (qfn),? on page 23. ? updated table 9, ?package diagram dimensions,? on page 23. ?? changed dimension a. ?? changed dimension e2. revision 1.2 to revision 1.3 ? table 2 on page 7. ?? updated power consumption. ?? updated r in . ? table 3 on page 8. ?? updated clock to data delay. ?? updated slicing level accuracy. ? table 4 on page 9. ?? updated tolerance. ?? updated acquisition time. ?? updated reference clock information. ? updated "6. ordering guide" on page 22. ?? added ?x? to part number. revision 1.3 to revision 1.4 ? updated table 2 on page 7. ?? added limits for v icm . ?? updated v od . ? updated table 3 on page 8. ?? updated t cr-d . ?? updated t cf-d . ?? revised slice specification. ? updated table 4 on page 9. ?? t aq min/max values updated. ? updated "4.7. loss-of-signal (los)" on page 13. ?? added note describing valid signal. ?? updated figure 6, ?los_lvl mapping,? on page 13. ? updated "4.9. data slicing level" on page 14. ?? added figure 8 on page 14. ?? revised text. revision 1.4 to revision 1.5 ? added "7. top mark" on page 22. ? updated "8. package outline" on page 23.
si5017 rev. 1.5 25 n otes :
si5017 26 rev. 1.5 c ontact i nformation silicon laboratories inc. 4635 boston lane austin, tx 78735 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: highspeed@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and om issions, and disclaims responsibi lity for any consequences resu lting from the use of information included herein. ad ditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laboratories products ar e not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or use silicon laboratorie s products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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